In Silicon-on-Insulator (SOI) transistor, a buried oxide layer is used, which isolates the body from the substrate shown in Figure 1(a). Thus, gates have a good control over the channel, which eliminates short channel effects. As the channel thickness is reduced, there are no paths, which are far from the gate area. In both transistor structures, the channel thickness scaling is introduced as the new scaling parameter. The main objective of both the structures is to maximize gate-to-channel capacitance and minimize drain-to-channel capacitance. The VLSI industry has adopted FinFET and SOI transistor for 16nm and 7nm nodes, as both the structures are able to prevent the leakage issue at these nodes. 16nm/7nm Transistor Technology: FinFet and FD-SOI:.As a result, the gate is unable to control leakage paths, which are far from the gate. Below this node, a horizontal electric field generated by drain-source supply tries to govern the channel. However, the short channel effects become uncontrollable if we shrink down CMOS transistor below 28 nm. The CMOS (complementary metal-oxide-semiconductor) transistor base IC technology performs well up to 28nm node. Scaling down a transistor enables faster switching, higher density, low power consumption, lower cost per transistor, and numerous other gains. We have seen transistor sizes such as 28nm, 16nm, etc. However, there are several challenges of scaling down a transistor size.Įvery time we scale down a transistor size, a new technology node is generated. Nowadays, the demand of the internet of things, autonomous vehicles, machine learning, artificial intelligence, and internet traffic is growing exponentially, which acts as a driving force for scaling down transistor below the existing 7nm node for higher performance. Some of these techniques are discussed in ‘A Review Paper on CMOS, SOI and FinFET Technology’. Various techniques, which have been adopted for transistors so far, include high-K dielectric, metal gate, strained silicon, double patterning, controlling channel from more than one side, silicon on insulator and many more techniques. To get the benefits of a scaled-down transistor, VLSI industry is continuously improving transistor structure and material, manufacturing techniques, and tools for designing IC. The VLSI industry is following Moore’s law for many decades, which says, “the number of transistors on a chip becomes double approximately every two years”. In an integrated circuit, all the active-passive components and their interconnection are integrated on a single silicon wafer, offering numerous advantages in terms of portability, functionality, power, and performance. The ‘Semiconductor era’ started in 1960 with the invention of the integrated circuit. Among them, this article reviews the potential transistor structures and materials like Carbon Nano-tube FET, Gate-All-Around FET, and Compound Semiconductors as solutions to overcome the problems of scaling the existing silicon FinFET transistor below 5nm node. Several researches are going on worldwide to overcome the challenges of future technology nodes. To scale down a transistor below a 5nm node is one of the vital concerns for VLSI industry as there are various challenges due to the shrinking of components. By Pavan H Vora, Akash Verma, Dhaval Parikh

Transistor size